1. Technical Field
The embodiment described herein relates to a semiconductor memory apparatus and, more particularly, to a semiconductor memory apparatus and a test circuit therefor.
2. Related Art
In order to realize high integration of semiconductor memory apparatuses, the semiconductor memory apparatuses are being implemented in an open bit-line structure (6F2).
Unlike known folded bit-line structures in which a bit-line and a bit-line-bar are provided in the same cell mat, the bit-line and the bit-line-bar are provided in different cell mats in open bit-line structures.
FIG. 1 is a diagram for illustrating a structure of a known open bit-line semiconductor memory apparatus.
As shown in the figure, the semiconductor memory apparatus includes a plurality of cell mats 10-1, 10-2, and 10-3 and each of the cell mats 10-1, 10-2, and 10-3 is provided with a plurality of memory cells C that are connected to word lines ‘WL0’ to ‘WLi’ and open bit-lines ‘BL0’ to ‘BLj’. Moreover, sense amplifier blocks 20-1 and 20-2 are disposed among the cell mats 10-1, 10-2, and 10-3. Bit-lines ‘BL0/BLb0’ to ‘BLj/BLbj’ connected to memory cells of two adjacent cell mats are commonly connected to sense amplifiers ‘SA’. That is, when the word line (for example, WL1) connected to the memory cell ‘C’ included in the cell mat 10-1 is selected and the bit-line (for example, ‘BL3’) is activated, the sense amplifier ‘SA’ amplifies and outputs data recorded in the corresponding memory cell depending on a potential difference between the bit-line ‘BL3’ connected to the corresponding memory cell ‘C’ and the bit-line-bar ‘BLb3’ existing in the adjacent cell mat 10-3. In such an open bit-line structure, in a test mode for checking whether or not each memory cell is defective, data recorded in all memory cells included in the cell mat 10-1 are amplified by the sense amplifier ‘SA’ and outputted through local input/output lines ‘LIO<0:n>/LIOb<0:n>’. Data outputted from the local input/output lines ‘LIO<0:n>/LIOb<0:n>’ are integrated into one data and whether or not the data are defective is checked.
If a predetermined memory cell ‘CF’ is defective, an integration result of data outputted from the local input/output line ‘LIO<0:n>/LIOb<0:n>’ that is connected with a first sense amplifier block 20-1 and a second sense amplifier block 20-2 is different from reference data. In this case, it is determined that the corresponding cell mat 10-1 is defective, such that a repair is performed for each cell mat. However, when the repair is performed, the bit-line and the bit-line-bar are repaired independently from each other or only one of two is repaired, such that reliability of the semiconductor memory apparatus is deteriorated.
Therefore, the cell mat 10-1 including the defective memory cell and the adjacent cell mats 10-2 and 10-3 which share the bit-line are repaired together. That is, in the case of the defective memory cell ‘CF’, although the bit-line exists in the first cell mat 10-1 and the bit-line-bar exists in the second cell mat 10-2, even a third cell mat 10-3 is repaired.
As such, whether or not the cell mats are defective is checked by integrating data of all memory cells included in each cell mat, where unnecessary cell mats are repaired. Therefore repair efficiency and yield are deteriorated.